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Celerity is an accelerator-centric system-on-chip (SoC) which uses a tiered accelerator fabric to improve energy efficiency in the context of high-performance embedded systems. The SoC is a 5 × 5 mm 385 M-transistor chip in TSMC 16 nm designed and implemented by a modest team of over 20 students and faculty from the University of Michigan, Cornell University, and the Bespoke Silicon Group (now at U. Washington) as part of the DARPA Circuit Realization At Faster Timescales (CRAFT) program. Celerity currently holds the world record for RISC-V performance; 500B RISC-V instructions per second, beating prior records by 100X.

SoC Top : bsg_design

Package & PCB : http://bjump.org

General Purpose Tier

A few fully featured RISC-V processors capable of running general-purpose software including an operating system. Modified version of Berkeley Rocket core.

• Rocket : bsg_rocket
• RoCC Doc: RoCC Doc V2

Massive Parallel Tier

A manycore comprising hundreds of lightweight RISC-V processors, a distributed shared memory system, and a mesh-based interconnect.

• BaseJump Manycore: bsg_manycore
• BaseJump STL: bsg_ip_cores
• Celerity QuickStart Tutorial

Specialization Tier

Application-specific accelerators (possibly generated using high-level synthesis).

• BNN FPGA: bnn-fpga