OpenCelerity

Open-Source RISC-V Tiered Accelerator Fabric SoC


click to see full figure
Celerity is an accelerator-centric system-on-chip (SoC) which uses a tiered accelerator fabric to improve energy efficiency in the context of high-performance embedded systems. The SoC is a 5 × 5 mm 385 M-transistor chip in TSMC 16 nm designed and implemented by a modest team of over 20 students and faculty from the University of Michigan, Cornell University, and the Bespoke Silicon Group at UC San Diego / U. Washington as part of the DARPA Circuit Realization At Faster Timescales (CRAFT) program.
SoC Top : bsg_design
Package & PCB : http://bjump.org

General Purpose Tier

A few fully featured RISC-V processors capable of running general-purpose software including an operating system. Modified version of Berkeley Rocket core.


Massive Parallel Tier

A manycore comprising hundreds of lightweight RISC-V processors, a distributed shared memory system, and a mesh-based interconnect.

Specialization Tier

Application-specific accelerators (possibly generated using high-level synthesis).